This application relates to integrated circuits, and more particularly to a circuit for creating a clock signal with a controllable pulse width.
Dynamic logic circuits are often used in modern integrated circuits. Decay or discharge of a non-driven node over time in a dynamic logic circuit can cause errors. To prevent these types of errors, it may be desirable to shorten one phase of a clock that regulates the timing of some dynamic circuits. By shortening this phase, the amount of time a node spends non-driven may be shortened without affecting the overall average clock cycle time, which may be critical to system performance.